The present invention relates to a nonvolatile semiconductor memory device in which data is electrically written/erased.
FIG. 1 is a sectional view of the memory cell of a conventional EEPROM.
As shown in FIG. 1, LOCOS element isolation regions 103 are formed in predetermined regions of a p-type silicon substrate 101, and the portion of the silicon substrate 101 present between the LOCOS element isolation regions 103 constitutes an element region 104. A tunnel oxide film 105 is formed in the element region 104, and a floating gate 106 is formed on the tunnel oxide film 105. An ONO insulating film 107 consisting of three silicon dioxide/silicon nitride/silicon dioxide layers is formed on the floating gate 106. A control gate 108 is formed on the ONO insulating film 107.
The data write/erase with respect to the memory cell shown in FIG. 1 will be explained using a NAND-type EEPROM as an example.
The NAND-type EEPROM uses a Fowler-Nordheim (FN) electric current for both a data write and data erase.
In writing data, a potential VPP is applied to a control gate selected for a write, a potential Vm is applied to a non-selected control gate and a selection gate, and the source region and the substrate 101 are grounded. The potential of the drain region is changed to either a positive potential or the ground potential depending on level "1" or "0" of the write data.
When the drain region is grounded, a potential is applied to positively bias the floating gate 106 side, and an FN electric current flows through the tunnel oxide film 105 to inject electrons from the substrate 101 side to the floating gate 106.
In erasing data, all control gates, selection gates, drain regions, and source regions selected for an erase are grounded, while a potential VEE is applied to the substrate 101.
In this potential state, a potential is applied to positively bias the substrate 101 side, and an FN electric current flows through the tunnel oxide film 105 to discharge electrons from the floating gate 106 to the substrate 101.
In the conventional memory cell, the amount of FN electric current passing through the tunnel oxide film 105 is determined by the electric field between the floating gate 106 and the substrate 101 generated by a voltage applied across the control gate 108 and the substrate 101. For this reason, e.g., to increase the write speed, the write voltage VPP applied across the control gate 108 and the substrate 101 must be increased to strengthen the electric field between the floating gate 106 and the substrate 101. If the write voltage VPP is raised, however, particularly the gate oxide film of a peripheral transistor must be made thick, so shrinking the whole EEPROM becomes problematic. If the write voltage VPP is raised too high, it is difficult to generate it inside the EEPROM.